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Voilà un post qui a suscité beaucoup d'intérêt sur le forum MacObserver. Le problème c'est que son auteur est resté anonyme et qu'on n'en sait pas beaucoup plus (m'enfin c'est déjà pas mal !!!)
Et désolé pour les anglophobes mais j'ai vraiment pas le courage de traduire tout ça
<BLOCKQUOTE><font size="1" face="Verdana, Geneva">quote:</font><HR>I am really discouraged that so few Mac fans understand the current state of PPC development, and where things are going. First let's talk about the Motorola side; here there is real information. Motorola holds information fairly closely, but not anywhere so closely as the total lack of comprehension here would make you think. Later I'll mention a few things about IBM, but this is more vaporware and long-term FUD.
First, some important basics: go read the two top articles about HIP-7 at chip-architect.com. You need to understand that Motorola and AMD are partners (with Moto being the tech lead) in their next-generation process development, 0.13 micron, Cu traces (duh), SOI (fancy), SiLK (fancy).
The second thing you need to do is to go and read Moto's public explanation of the G4+ architecture at
http://e-www.motorola.com/brdata/PDFDB/MICROPROCESSORS/32_BIT/POWERPC/MPC7XX/MPC7450FACT.pdf
but the really salient thing to understand is that the G4+ is the first major revision of the fundamental G3/G4 core created by the combined IBM/Moto Somerset design team (the scalar core of the G3 and G4 are nearly identical functionally), and that the G4+ architecture deepens the pipeline depth to 7 (from 4 on all earlier G3/G4 PPC) and adds execution units to both the scalar core and the Altivec unit (separate Vector-permute unit in that case). It also greatly increases rename registers, and improves instruction dispatch and retirement.
Putting this in the simplest light, the scalar core of the G4+ is considerably more "Athlon like" than the previous PPC processors. In a variety of ways, particularly Altivec, it is more advanced than Athlon.
The current MPC7450 (aka G4+, aka V'ger) is built in HIP-6 (0.18 micron, Cu). During the runnup to the G4+ introduction Motorola publicly disclosed some design/development criteria for the MPC7450 as it was designed for HIP-6, including design goals for clock-skew through the system. These are coupled to the absolute top "headroom" frequency (given number of pipeline stages, and some other considerations.) The Motorola clock-skew figures, which they met, mean that the engineers were designing the MPC7450 so that clock-skew variation wouldn't be limiting until roughly 1.1 to 1.2 GHz. This makes it very clear that Motorola was building performance headroom into the MPC7450, even on HIP-6.
The current AMD production process for Athlons (A 6-layer damascene process which it basically "inherited" from IBM, by way of NextGen which was a IBM spin-off (or out) of IBM's 686 processor, the last x86 processor IBM designed but didn't want to build) is similar in gate rules to HIP-6.
However, AMD's transistors are optimized for higher voltage and speed (meaning more heat produced) than Moto's reflecting their differing markets, and AMD's Athlons use more metal layers (also more than Intel's P3s) which gives more routing freedom and cut some propagation delays. More layers cost more, which AMD partially recoupes through volume, and partially through higher prices.
Further of course the Athlon processors are very production-mature and there has been a long succession of process and mask tweaks to get to the current 1.2 - 1.4 Ghz status.
For all of these reasons no one should expect the existing MPC7450 to "jump" to 1 Ghz or beyond quickly, but it is widely known that Motorola is getting excellent yields at well above 766 MHz (part of why Apple killed the 667 Mac, very quickly Moto stopped making parts which needed to be graded that slow) I think we may see 833 - 900 MHz Mac towers using the MPC7450 announced at MWNY.
Now, going back to HIP-7, Motorola announced last year that HIP-7 was a major initiative for them, and that they were going to push to this technology as fast as they could, and that the first major product would be "Apollo," the G4+ architecture implemented in this new process (again, 0.13 micron, Cu, SOI, SiLK) Motorola announced at the last Microprocessor Forum that these parts should debut at 1 GHz and scale up from there. (The existing MPC7450 might be able to get to 1 GHz on HIP-6, but that would be pushing it without a re-layout and also transistor reoptimization, and they would be HOT at 1 GHz... like Athlons).
An important point: "Apollo" is NOT G5. G5 is further back, and is a more complex revision, including multiple cores on one die. "Apollo" is G4+ (with only limited architectural tweaks) built on HIP-7. This is good, because it means that there aren't logical/functional issues to sort out; the MPC7450 is catching those. Apollo we may have soon, don't hold your breath for G5.
Very trustworthy recent reports describe Moto demoing early working cpus at 1 GHz and over; presumptively these must be early prototype "Apollo" parts. Less reliable sources describe Apple demoing machines with 1 GHz CPUs.... certainly ditto if true ( The memory on which these machines are running was not disclosed, more about that later.)
What rumors do leak out are optimistic about Moto's progress with HIP-7, but one needs to be cautious about buying into these because there is obviously a self-serving reason to leak this kind of stuff.
An optimist however might predict an Apple announcement at MWNY of machines at 1 GHz based on Apollo, rather like this winter's announcement of the G4+, based on early silicon and to be delivered in a month or two. Most motorola watchers thought the G4+ was about 3 mos away then, and most moto watchers now think Apollo is mid to late summer.
Having covered what is on-tap from Moto, I want to step back a moment, because the fact that Moto can build CPUs, DOESN'T guarantee that Apple will build good computers with them. The major performance limitation of Apple's top-end computers right now *isn't* CPUs ... it is memory. The Pentium 4 is a terrible processor on PC133; RDRAM (or DDR coming soon) is necessary for it to have any advantage over the P3. The top-end AMD systems are all going to DDR.
Many, many people have pointed out the obvious truth from a hardware perspective: Apple can buy TWO MPC7450s for less than the current price of a Pentium4, that this will consume 20 Watts LESS power, and given MEMORY BANDWIDTH this solution will outrun the P4 at many problems (at a price though. It is harder to code for multi-processors efficiently and it is significantly harder at present to write good code for Altivec.)
Another comment here is that the MPC7440 (basically a cut-down MPC7450 without the external L3 cache interface) looks to me like an excellent solution for some niches that Apple might build (particularly laptops and duals). Apple enthusiasts have been sneering at this chip as a "Celeron." Nonsense: this chip still has the 256 kB on-chip L2 cache. For perspective this ALL the cache that a P4 has. It is also all the cache that most Athlon and Athlon derivatives have.
The external L3 cache is fairly expensive for Apple to implement, both in extra cost for the high-speed SRAM needed, and testing/QC issues. For a buck, a dual MPC7440 system could be very attractive. A lot of the reason that Macs NEED all that extra cache is that it can partially offset the effects of being down on cycles and down on memory bandwidth. But large external SRAM caches are a very expensive and only partially-effective way of doing this.
The reality is that current Apple machines are memory-bandwidth starved. This post is being written on a DP533: two MPC7410s running at 533 MHz on PC133. For most of the altivec algorithms I develop there is no advantage to making them MP and using the second CPU ... except for the subtle advantage that by doing so I pick up another 1 Mb of cache. There are several reasons we haven't seen dual MPC7450 machines yet (though I expect them at MWNY, of a near certainty), a long list of errata affecting MP was among these until recently. But a nasty reality for Apple is that a dual 800+ MHz MPC7450 system will not have much advantage over a single if PC133 is all the memory there is, on the Altivec-dependent P'shop algorithms that Steve likes to demo.
There are of course lots of real-world problems (servers being a classic one) where two CPUs would make good sense even if limited to PC133, but the Apple fans don't respond to server demos.
So Apple NEEDS better memory than PC133, and it needs it right about now. Folks may remember that all the Apple blather sites were claiming we would get DDR with the first G4+ machines... and we didn't. After that we got a pile of embarrassed 180 degree turn-around and cover-up and apple-pologists claiming that the G4+ wouldn't work with DDR! (nonsense even tho the current MPC7450 fact sheet talks about "133 MHz FSB"). The real facts are that the MPX bus itself isn't intimately memory-timing coupled, and on any MPC7450 at 733 Mhz and faster the MPX bus transfers can occur quickly enough to take full advantage of PC2100 (133 MHz DDR), but a completely new memory interface controller (aka "northbridge" in PC parlance) is required.
The rumor-mill sites have been blathering for over a year about a "Uni-North 2.0" which they claim Apple is developing for DDR. Mac fans had better hope this is true and that Apple is close to production. Otherwise real performance improvement on the bandwidth intensive algorithms will stall, and all Mac folks will get are "useless MHz."
With DDR Apple will still have "a MHz problem" because P4 will be up to 2 GHz pretty shortly. "Athlons" will be up around 1.5 GHz. But Apple won't have any REAL performance problem. Apple can afford dual PPC solutions at lower price and power points than the x86 competion. osX will use these to excellent advantage. A 1+ GHz Apollo should reasonably hold its own against the Athlons or P4s ... GIVEN decent memory. There is no reason to fear for real performance so long as Apple rolls out a DDR chipset shortly. Without DDR Apple will be in serious trouble.
I now want to talk just a bit about IBM, and some other more speculative topics. The following is taken from another post I placed elsewhere:
*****
IBM hasn't really invested much of anything in desktop-level PPC ever sense AIM died. IBM competes for "desktop" customers with Apple. It is obvious that there are business units within IBM who see crippled desktop-level PPC as a good thing, not bad. However, with IBM's PC division disolving into disastrous losses, and the DOJ vs. MS decision opening up some room in marketspace, IBM appears to be reconsidering its longer term strategy. The "cell" initiative might come to something (whether this would benefit Apple remains TBD). At the moment the fact remains that Apple has only one vendor (motorola) for its top-end systems and that IBM simply builds cheap stuff for "consumer." You wouldn't think this is the way it should be given IBM's technology prowess, but it is reality, at least for the next year or two, because a major microprocessor design cycle takes that long.
[ IBM stated they will achieve 1 Ghz by the end of the year and 2 Ghz by the end of 2002 for their embedded PowerPC chips. ]
I'm not holding my breath. They said they'd have the IBM750CXe (the G3 in the iMacs and iBooks) at 750 Mhz a year ago.
[This would leave only six months left for essentially doubling the current 500 Mhz on the IBM side. Apple could announce a faster iMac in July, that would go on the market in August, for somewhat higher Mhz IBM chips. ]
IBM makes 700 MHz G3s right now. They cost alot, about what top MPC7450s do. For all but *very* unusual problems the IBM G3 gets run over in its tracks by the MPC7450 at equal MHz on equal memory.
Today's iMacs all use the 500 MHz IBM G3 (the slowest part IBM sells) solely because it is cheap, it keeps a second vendor around for Apple (gotta have it) and so Apple needs to sell something that can use that chip, and because on PC100 (or worse yet the 66 MHz of the ibook) more MHz isn't going to yield anything like proportional performance.
[ Neither IBM nor Motorola make a desktop PowerPC processor for the mass market. These recent announcements of speed increases for their chips is due to the higher performance demands in the embedded market and the competition between each other for these customers. ]
This is an oxymoronic statement. There isn't any non-x86 "mass market" so it is impossible for either of these vendors to make anything that meets your criterion! You have just bought into the ranting "embedded is no good" hype.
The MPC7450 was basically built for Apple, and the hope that the embedded market would "catch up to it," when the HIP-7 parts come around. Right now almost nobody is using the 7450 for embedded: it runs too hot for most embedded applications, and the support chips aren't there. This latter issue is a sore point with me: I don't see any reason to go to the expense of the 7450 on PC100, but that is all the MPC107 (or Gallileo, or Tundra) chipsets support.
[ By virtue of using processors designed for the embedded market, Apple will be using chips that are perhaps half the Mhz of their competition on the desktop, for at least until the end of 2002. ]
You are talking MHz, not real performance. Pentium4 at 2 Ghz isn't anything like twice as fast as Pentium3 at 1 GHz, more like 30% on typical Wintel instruction mix, and that given RDRAM for the P4.
Apple is going to have a "MHz problem" relative to Pentium4... but then so is AMD. The Wintel folks are starting to discover that MHz aren't created equal. In many ways the P4 is the best thing that ever happened to Apple.
The new G4+ architecture is very "Athlon like" internally, without the x86 decode unit obviously (an advantage). On HIP-7 the G4+ should converge to Athlon/Hammer clock speeds. A subtle reason for this is that as the transistors shrink, wires don't shrink. As a design is "shrunk" it becomes more wire-bound. All 0.13 micron layouts are going to more metal layers. AMD and Moto are going to be converging for better or worse. If the G4+ doesn't scale well to HIP-7 then AMD will be in trouble too. Moto is the technical lead in this pair, and the G4+ stuff is going through the HIP-7 process before Hammer. At equal clock speeds the G4+ architecture should beat Athlon/Hammer; clobbering it for anything Altivec can do.
[ They look to be much more efficient performers than the competitors by virtue of the demands of the embedded market. This would help considerably in price/performance on portables, but would mean little on the desktop. ]
Not so. It means that you can have a dual cheaper and at a lower power point than the competitors.
[ IBM is perfectly willing to use their fabrication facilities to make a processor for their competitors and they will even recommend a product that they do not sell, to try and make themselves a one stop company for their customers. This has been going on for three or four years under their new CEO. The competitors were extremely sceptical about getting equal treatment to the IBM chips being fabricated, but IBM has been able to reassure them that they will be handled in the same manner. ]
IBM has been selling foundry services. This means tho that "somebody" needed to design the chip. IBM's foundry services "rescued" AMD when it had yield problems with the early K-7 (otherwise the Athlon wouldn't exist today) and alleviated Moto's and Apple's problem with the MPC7400 production before the MPC7410. Both companies paid deeply for their "rescue."
But so far IBM hasn't put any significant design resources into lower end PPC except for designs which poach on Motorola's embedded customers. The recent IBM claims of much faster chips may represent a change of heart/plans for IBM, or they may be just more IBM FUD and spin. We will need to wait and see.
There are far too many extremely foolish posts suggesting that Apple should ditch PPC for Athlons, or Alphas (which Apple couldn't possibly afford in it's markup structure), or whatever processor is hype du jour for that poster. (People who think Apple could have a business on the Power4 are so ill-informed about reality as to make me wonder about their sanity.) This is all nonsense: the cost of a changeover would be unbearable both for Apple and for all its users and support tier (with one possible exception noted below). And switching to x86 would just leave Apple as another me-too x86 producer, giving away what are at present PPC advantages of cost and low power. Apple is "stuck" with PPC, and Apple must manage its relations with Motorola and IBM so that it gets the processors it needs. In this connection Apple continues to pay the lingering price for destroying the AIM consortium and the ill-will it accrued from IBM (and secondarily Motorola) by doing so.
The only CPU "bailout" or "escape" strategy I see for Apple would be to get a powerful enough "dynamic recompilation" (aka "code morphing" etc) capability that it could jump to another processor and maintain code functionality for existing code at acceptable performance levels. Similarly if this could be done it would also permit much more acceptable emulation of x86. If I were in any position of authority at Apple I would be researching dynamic recompilation strategies for all they were worth as a safety net. But I think in the long run though that dynamic cross-CPU recompilation will generally not outperform dynamic re-optimization on CPU, clearly a coming thing. The major advantage of this strategy is that it may make VLIW architectures viable. This is the Transmeta strategy. IMO Transmeta, and efforts of this general kind, are the things to watch. Right now the Crusoe doesn't really have any edge over PPC (except for emulating x86!), but the game is still young.<HR></BLOCKQUOTE>
Forum MacObserver
Bon ben si ça s'avérait vrai ça pourrait être pas mal pour Apple... s'ils mettaient de la DDRAM sur les prochains mac bien sûr.
Et désolé pour les anglophobes mais j'ai vraiment pas le courage de traduire tout ça
<BLOCKQUOTE><font size="1" face="Verdana, Geneva">quote:</font><HR>I am really discouraged that so few Mac fans understand the current state of PPC development, and where things are going. First let's talk about the Motorola side; here there is real information. Motorola holds information fairly closely, but not anywhere so closely as the total lack of comprehension here would make you think. Later I'll mention a few things about IBM, but this is more vaporware and long-term FUD.
First, some important basics: go read the two top articles about HIP-7 at chip-architect.com. You need to understand that Motorola and AMD are partners (with Moto being the tech lead) in their next-generation process development, 0.13 micron, Cu traces (duh), SOI (fancy), SiLK (fancy).
The second thing you need to do is to go and read Moto's public explanation of the G4+ architecture at
http://e-www.motorola.com/brdata/PDFDB/MICROPROCESSORS/32_BIT/POWERPC/MPC7XX/MPC7450FACT.pdf
but the really salient thing to understand is that the G4+ is the first major revision of the fundamental G3/G4 core created by the combined IBM/Moto Somerset design team (the scalar core of the G3 and G4 are nearly identical functionally), and that the G4+ architecture deepens the pipeline depth to 7 (from 4 on all earlier G3/G4 PPC) and adds execution units to both the scalar core and the Altivec unit (separate Vector-permute unit in that case). It also greatly increases rename registers, and improves instruction dispatch and retirement.
Putting this in the simplest light, the scalar core of the G4+ is considerably more "Athlon like" than the previous PPC processors. In a variety of ways, particularly Altivec, it is more advanced than Athlon.
The current MPC7450 (aka G4+, aka V'ger) is built in HIP-6 (0.18 micron, Cu). During the runnup to the G4+ introduction Motorola publicly disclosed some design/development criteria for the MPC7450 as it was designed for HIP-6, including design goals for clock-skew through the system. These are coupled to the absolute top "headroom" frequency (given number of pipeline stages, and some other considerations.) The Motorola clock-skew figures, which they met, mean that the engineers were designing the MPC7450 so that clock-skew variation wouldn't be limiting until roughly 1.1 to 1.2 GHz. This makes it very clear that Motorola was building performance headroom into the MPC7450, even on HIP-6.
The current AMD production process for Athlons (A 6-layer damascene process which it basically "inherited" from IBM, by way of NextGen which was a IBM spin-off (or out) of IBM's 686 processor, the last x86 processor IBM designed but didn't want to build) is similar in gate rules to HIP-6.
However, AMD's transistors are optimized for higher voltage and speed (meaning more heat produced) than Moto's reflecting their differing markets, and AMD's Athlons use more metal layers (also more than Intel's P3s) which gives more routing freedom and cut some propagation delays. More layers cost more, which AMD partially recoupes through volume, and partially through higher prices.
Further of course the Athlon processors are very production-mature and there has been a long succession of process and mask tweaks to get to the current 1.2 - 1.4 Ghz status.
For all of these reasons no one should expect the existing MPC7450 to "jump" to 1 Ghz or beyond quickly, but it is widely known that Motorola is getting excellent yields at well above 766 MHz (part of why Apple killed the 667 Mac, very quickly Moto stopped making parts which needed to be graded that slow) I think we may see 833 - 900 MHz Mac towers using the MPC7450 announced at MWNY.
Now, going back to HIP-7, Motorola announced last year that HIP-7 was a major initiative for them, and that they were going to push to this technology as fast as they could, and that the first major product would be "Apollo," the G4+ architecture implemented in this new process (again, 0.13 micron, Cu, SOI, SiLK) Motorola announced at the last Microprocessor Forum that these parts should debut at 1 GHz and scale up from there. (The existing MPC7450 might be able to get to 1 GHz on HIP-6, but that would be pushing it without a re-layout and also transistor reoptimization, and they would be HOT at 1 GHz... like Athlons).
An important point: "Apollo" is NOT G5. G5 is further back, and is a more complex revision, including multiple cores on one die. "Apollo" is G4+ (with only limited architectural tweaks) built on HIP-7. This is good, because it means that there aren't logical/functional issues to sort out; the MPC7450 is catching those. Apollo we may have soon, don't hold your breath for G5.
Very trustworthy recent reports describe Moto demoing early working cpus at 1 GHz and over; presumptively these must be early prototype "Apollo" parts. Less reliable sources describe Apple demoing machines with 1 GHz CPUs.... certainly ditto if true ( The memory on which these machines are running was not disclosed, more about that later.)
What rumors do leak out are optimistic about Moto's progress with HIP-7, but one needs to be cautious about buying into these because there is obviously a self-serving reason to leak this kind of stuff.
An optimist however might predict an Apple announcement at MWNY of machines at 1 GHz based on Apollo, rather like this winter's announcement of the G4+, based on early silicon and to be delivered in a month or two. Most motorola watchers thought the G4+ was about 3 mos away then, and most moto watchers now think Apollo is mid to late summer.
Having covered what is on-tap from Moto, I want to step back a moment, because the fact that Moto can build CPUs, DOESN'T guarantee that Apple will build good computers with them. The major performance limitation of Apple's top-end computers right now *isn't* CPUs ... it is memory. The Pentium 4 is a terrible processor on PC133; RDRAM (or DDR coming soon) is necessary for it to have any advantage over the P3. The top-end AMD systems are all going to DDR.
Many, many people have pointed out the obvious truth from a hardware perspective: Apple can buy TWO MPC7450s for less than the current price of a Pentium4, that this will consume 20 Watts LESS power, and given MEMORY BANDWIDTH this solution will outrun the P4 at many problems (at a price though. It is harder to code for multi-processors efficiently and it is significantly harder at present to write good code for Altivec.)
Another comment here is that the MPC7440 (basically a cut-down MPC7450 without the external L3 cache interface) looks to me like an excellent solution for some niches that Apple might build (particularly laptops and duals). Apple enthusiasts have been sneering at this chip as a "Celeron." Nonsense: this chip still has the 256 kB on-chip L2 cache. For perspective this ALL the cache that a P4 has. It is also all the cache that most Athlon and Athlon derivatives have.
The external L3 cache is fairly expensive for Apple to implement, both in extra cost for the high-speed SRAM needed, and testing/QC issues. For a buck, a dual MPC7440 system could be very attractive. A lot of the reason that Macs NEED all that extra cache is that it can partially offset the effects of being down on cycles and down on memory bandwidth. But large external SRAM caches are a very expensive and only partially-effective way of doing this.
The reality is that current Apple machines are memory-bandwidth starved. This post is being written on a DP533: two MPC7410s running at 533 MHz on PC133. For most of the altivec algorithms I develop there is no advantage to making them MP and using the second CPU ... except for the subtle advantage that by doing so I pick up another 1 Mb of cache. There are several reasons we haven't seen dual MPC7450 machines yet (though I expect them at MWNY, of a near certainty), a long list of errata affecting MP was among these until recently. But a nasty reality for Apple is that a dual 800+ MHz MPC7450 system will not have much advantage over a single if PC133 is all the memory there is, on the Altivec-dependent P'shop algorithms that Steve likes to demo.
There are of course lots of real-world problems (servers being a classic one) where two CPUs would make good sense even if limited to PC133, but the Apple fans don't respond to server demos.
So Apple NEEDS better memory than PC133, and it needs it right about now. Folks may remember that all the Apple blather sites were claiming we would get DDR with the first G4+ machines... and we didn't. After that we got a pile of embarrassed 180 degree turn-around and cover-up and apple-pologists claiming that the G4+ wouldn't work with DDR! (nonsense even tho the current MPC7450 fact sheet talks about "133 MHz FSB"). The real facts are that the MPX bus itself isn't intimately memory-timing coupled, and on any MPC7450 at 733 Mhz and faster the MPX bus transfers can occur quickly enough to take full advantage of PC2100 (133 MHz DDR), but a completely new memory interface controller (aka "northbridge" in PC parlance) is required.
The rumor-mill sites have been blathering for over a year about a "Uni-North 2.0" which they claim Apple is developing for DDR. Mac fans had better hope this is true and that Apple is close to production. Otherwise real performance improvement on the bandwidth intensive algorithms will stall, and all Mac folks will get are "useless MHz."
With DDR Apple will still have "a MHz problem" because P4 will be up to 2 GHz pretty shortly. "Athlons" will be up around 1.5 GHz. But Apple won't have any REAL performance problem. Apple can afford dual PPC solutions at lower price and power points than the x86 competion. osX will use these to excellent advantage. A 1+ GHz Apollo should reasonably hold its own against the Athlons or P4s ... GIVEN decent memory. There is no reason to fear for real performance so long as Apple rolls out a DDR chipset shortly. Without DDR Apple will be in serious trouble.
I now want to talk just a bit about IBM, and some other more speculative topics. The following is taken from another post I placed elsewhere:
*****
IBM hasn't really invested much of anything in desktop-level PPC ever sense AIM died. IBM competes for "desktop" customers with Apple. It is obvious that there are business units within IBM who see crippled desktop-level PPC as a good thing, not bad. However, with IBM's PC division disolving into disastrous losses, and the DOJ vs. MS decision opening up some room in marketspace, IBM appears to be reconsidering its longer term strategy. The "cell" initiative might come to something (whether this would benefit Apple remains TBD). At the moment the fact remains that Apple has only one vendor (motorola) for its top-end systems and that IBM simply builds cheap stuff for "consumer." You wouldn't think this is the way it should be given IBM's technology prowess, but it is reality, at least for the next year or two, because a major microprocessor design cycle takes that long.
[ IBM stated they will achieve 1 Ghz by the end of the year and 2 Ghz by the end of 2002 for their embedded PowerPC chips. ]
I'm not holding my breath. They said they'd have the IBM750CXe (the G3 in the iMacs and iBooks) at 750 Mhz a year ago.
[This would leave only six months left for essentially doubling the current 500 Mhz on the IBM side. Apple could announce a faster iMac in July, that would go on the market in August, for somewhat higher Mhz IBM chips. ]
IBM makes 700 MHz G3s right now. They cost alot, about what top MPC7450s do. For all but *very* unusual problems the IBM G3 gets run over in its tracks by the MPC7450 at equal MHz on equal memory.
Today's iMacs all use the 500 MHz IBM G3 (the slowest part IBM sells) solely because it is cheap, it keeps a second vendor around for Apple (gotta have it) and so Apple needs to sell something that can use that chip, and because on PC100 (or worse yet the 66 MHz of the ibook) more MHz isn't going to yield anything like proportional performance.
[ Neither IBM nor Motorola make a desktop PowerPC processor for the mass market. These recent announcements of speed increases for their chips is due to the higher performance demands in the embedded market and the competition between each other for these customers. ]
This is an oxymoronic statement. There isn't any non-x86 "mass market" so it is impossible for either of these vendors to make anything that meets your criterion! You have just bought into the ranting "embedded is no good" hype.
The MPC7450 was basically built for Apple, and the hope that the embedded market would "catch up to it," when the HIP-7 parts come around. Right now almost nobody is using the 7450 for embedded: it runs too hot for most embedded applications, and the support chips aren't there. This latter issue is a sore point with me: I don't see any reason to go to the expense of the 7450 on PC100, but that is all the MPC107 (or Gallileo, or Tundra) chipsets support.
[ By virtue of using processors designed for the embedded market, Apple will be using chips that are perhaps half the Mhz of their competition on the desktop, for at least until the end of 2002. ]
You are talking MHz, not real performance. Pentium4 at 2 Ghz isn't anything like twice as fast as Pentium3 at 1 GHz, more like 30% on typical Wintel instruction mix, and that given RDRAM for the P4.
Apple is going to have a "MHz problem" relative to Pentium4... but then so is AMD. The Wintel folks are starting to discover that MHz aren't created equal. In many ways the P4 is the best thing that ever happened to Apple.
The new G4+ architecture is very "Athlon like" internally, without the x86 decode unit obviously (an advantage). On HIP-7 the G4+ should converge to Athlon/Hammer clock speeds. A subtle reason for this is that as the transistors shrink, wires don't shrink. As a design is "shrunk" it becomes more wire-bound. All 0.13 micron layouts are going to more metal layers. AMD and Moto are going to be converging for better or worse. If the G4+ doesn't scale well to HIP-7 then AMD will be in trouble too. Moto is the technical lead in this pair, and the G4+ stuff is going through the HIP-7 process before Hammer. At equal clock speeds the G4+ architecture should beat Athlon/Hammer; clobbering it for anything Altivec can do.
[ They look to be much more efficient performers than the competitors by virtue of the demands of the embedded market. This would help considerably in price/performance on portables, but would mean little on the desktop. ]
Not so. It means that you can have a dual cheaper and at a lower power point than the competitors.
[ IBM is perfectly willing to use their fabrication facilities to make a processor for their competitors and they will even recommend a product that they do not sell, to try and make themselves a one stop company for their customers. This has been going on for three or four years under their new CEO. The competitors were extremely sceptical about getting equal treatment to the IBM chips being fabricated, but IBM has been able to reassure them that they will be handled in the same manner. ]
IBM has been selling foundry services. This means tho that "somebody" needed to design the chip. IBM's foundry services "rescued" AMD when it had yield problems with the early K-7 (otherwise the Athlon wouldn't exist today) and alleviated Moto's and Apple's problem with the MPC7400 production before the MPC7410. Both companies paid deeply for their "rescue."
But so far IBM hasn't put any significant design resources into lower end PPC except for designs which poach on Motorola's embedded customers. The recent IBM claims of much faster chips may represent a change of heart/plans for IBM, or they may be just more IBM FUD and spin. We will need to wait and see.
There are far too many extremely foolish posts suggesting that Apple should ditch PPC for Athlons, or Alphas (which Apple couldn't possibly afford in it's markup structure), or whatever processor is hype du jour for that poster. (People who think Apple could have a business on the Power4 are so ill-informed about reality as to make me wonder about their sanity.) This is all nonsense: the cost of a changeover would be unbearable both for Apple and for all its users and support tier (with one possible exception noted below). And switching to x86 would just leave Apple as another me-too x86 producer, giving away what are at present PPC advantages of cost and low power. Apple is "stuck" with PPC, and Apple must manage its relations with Motorola and IBM so that it gets the processors it needs. In this connection Apple continues to pay the lingering price for destroying the AIM consortium and the ill-will it accrued from IBM (and secondarily Motorola) by doing so.
The only CPU "bailout" or "escape" strategy I see for Apple would be to get a powerful enough "dynamic recompilation" (aka "code morphing" etc) capability that it could jump to another processor and maintain code functionality for existing code at acceptable performance levels. Similarly if this could be done it would also permit much more acceptable emulation of x86. If I were in any position of authority at Apple I would be researching dynamic recompilation strategies for all they were worth as a safety net. But I think in the long run though that dynamic cross-CPU recompilation will generally not outperform dynamic re-optimization on CPU, clearly a coming thing. The major advantage of this strategy is that it may make VLIW architectures viable. This is the Transmeta strategy. IMO Transmeta, and efforts of this general kind, are the things to watch. Right now the Crusoe doesn't really have any edge over PPC (except for emulating x86!), but the game is still young.<HR></BLOCKQUOTE>
Forum MacObserver
Bon ben si ça s'avérait vrai ça pourrait être pas mal pour Apple... s'ils mettaient de la DDRAM sur les prochains mac bien sûr.
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